Data storage memory is one of the backbones of the modern information technology. Semiconductor memory in the form of Dynamic random-access memory (DRAM), Static random-access memory (SRAM) and flash memory has dominated the digital world for the last forty years. Comparing to DRAM based on transistor and capacitor, SRAM using the state of a flip-flop with large form factor is more expensive to produce but generally faster and less power consumption. Nevertheless, both DRAM and SRAM are volatile memory, which means they lost the information stored once the power is removed. Flash memory on the other hand is non-volatile memory and cheap to manufacture. However, flash memory has limited endurances of writing cycle and slow write though the read is relatively faster.
MRAM is relatively a new type of memory technology. It has the speed of the SRAM, density of the DRAM and it is non-volatile as well. If it is used to replace the DRAM in computer, it will not only give “instant on” but “always-on” status for operation system, and restore the system to the point when the system is power off last time. It could provide a single storage solution to replace separate cache (SRAM), memory (DRAM) and permanent storage (hard disk drive (HDD) or flash-based solid state drive (SSD)) on portable device at least. Considering the rapid growth of “cloud computing” technology, MRAM has a great potential and can be the key dominated technology in digital world.
MRAM stores the informative bit “1” or “0” into the two magnetic states in the so-called magnetic storage layer. The different states in the storage layer give two distinctive voltage outputs from the whole memory cell, normally a patterned TMR stack. The TMR stack provides a read out mechanism sharing the same well-understood physics as current magnetic reader used in conventional hard disk drive.
There are two kinds of existing MRAM technologies based on the write process: one kind, which can be labeled as the conventional magnetic field switched (toggle) MRAM, uses the magnetic field induced by the current in the remote write line to change the magnetization orientation in the data stored magnetic layer from one direction (i.e. “1”) to the opposite direction (i.e. “0”). This kind of MRAM has more complicated cell structure and needs relative high write current (in the order of mA). It also has poor scalability beyond 65 nm because the write current in the write line needs to continue increase to ensure reliable switching the magnetization of the magnetic storage layer because of the fact that the smaller the physical dimension of the storage layer, the higher the magnetic coercivity it normally has for the same material. Nevertheless, the only commercially available MRAM so far is still based on this conventional writing scheme. The other class of the MRAM is called spin-transfer torque (STT) switching MRAM. It is believed that the STT-RAM has much better scalability due to its simple memory cell structure. While the data read out mechanism is still based on TMR effect, the data write is governed by physics of spin-transfer effect (J. C. Slonczewski, J. Magn. Magn. Mater. 159, (1996) L1.; L. Berger, Phys. Review B 54 (1996) 9353.). Despite of intensive efforts and investment, even with the early demonstrated by Sony in late 2005 (M. Hosomi et al., 2005 IEDM Technical Digest (2005) p 459), no commercial products are available on the market so far. One of the biggest challenges of STT-RAM is its reliability, which depends largely on the value and statistical distribution of the critical current density needed to flip the magnetic storage layers within every patterned TMR stack used in the MRAM memory structures. Currently, the value of the critical current density is still in the range of 106 A/cm2. To allow such large current density through the dielectric barrier layer such as AlOx and MgO in the TMR stack, the thickness of the barrier has to be relatively thin, which not only limits the magnetoresist (MR) ratio value but also causes potential risk of the barrier breakdown. As such, a large portion of efforts in developing the STT-RAM is focused on lower the critical current density while still maintaining the thermal stability of the magnetic data storage layer. Another challenge is related partially to the engineering challenge due to the imperfection of the memory cell structure patterning (patterned TMR element), such as edge magnetic moment damage, cell size variation, non-uniformity of the barrier thickness, non-uniformity of magnetic properties in both the data storage layer and the spin polarized magnetic layer (also called reference layer). Such imperfections ultimately cause the statistic variation of critical current density needed for each patterned cell.
The success of the STT-RAM largely depends on the materials used in STT-RAM, which should give a fair balance between the barrier thickness (related to broken down voltage and TMR ratio), critical current density and thermal stability of the magnetic storage layer.
In this invention, we propose two new MRAM memory cell structures with a new write mechanism based on the latest finding by I. M. Miron et al. (I. M. Miron et. al, Nature 476, (2011) 189). The advantages of the our new designs are: 1) write current does not pass through TMR barrier as the conventional MRAM does to avoid the reliability concerns of STT-RAM; 2) the cell structure is simpler than the conventional MRAM as it does not need toggle write scheme; 3) one of our designs has a very good scalability; 4) the other of our designs decouples the read and write elements. This means that we can individually optimize the read and write components. For example, we can focus on improvement of the MR ratio of read element while, for write element, we can put emphasis on the reliable switching.